1. Field of the Invention
The present invention relates generally to microelectronic structures and fabrication methods, and more particularly to an unlanded via structure and methods of making the same.
2. Background
Advances in semiconductor manufacturing technology have led to the development of integrated circuits having multiple levels of interconnect. In such an integrated circuit, patterned conductive material on one interconnect level is electrically insulated from patterned conductive material on another interconnect level by films of material such as silicon dioxide. Connections between the conductive material at the various interconnect levels are made by forming openings in the insulating layers and providing an electrically conductive structure such that the patterned conductive material from different interconnect levels are brought into electrical contact with each other. These structures are often referred to contacts or vias.
A consequence of having multiple layers of patterned conductive material separated by an insulating layer is the formation of undesired capacitors. The parasitic capacitance between patterned conductive material, or more simply, interconnects, separated by insulating material on microelectronic devices contributes to effects such as RC delay, power dissipation, and capacitively coupled signals, also known as cross-talk.
One way to reduce the unwanted capacitance between the interconnects is to use an insulating material with a lower dielectric constant. Unfortunately, low dielectric constant materials tend to not have sufficient mechanical strength to support the multi-level interconnect systems typical of complex integrated circuits. A hybrid approach is possible wherein an intra-layer low dielectric constant material is disposed between the interconnect lines and planarized, and then a layer of mechanically stronger but electrically less desirable material is formed as an inter-layer dielectric.
Another issue that confronts manufacturers of integrated circuits is that of packing density. One aspect of packing density, often referred to as pitch, is the width of an interconnect line and the space required between those lines. When a via is formed between two interconnect levels it has been required that there be overlap of the opening by the underlying conductive material. In some cases this requires that the minimum width of the underlying conductive material be increased to provide a landing for the via opening. FIG. 1 shows a schematic cross-section of a landed via between metal lines on two different interconnect levels. The increase in minimum width to accommodate the overlap requirement increases the pitch, and correspondingly decreases the packing density.
A way of reducing the pitch is to remove the requirement of having a landed via. That is, unlanded vias offer increased packing density. However, the process of unlanded via formation has proved to be incompatible with the hybrid low-dielectric constant intra-layer material capped with a mechanically stronger inter-layer dielectric.
What is needed is a structure that supports high packing density while simultaneously providing low parasitic capacitance between interconnect layers, and methods of making such a structure.